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TECHNICAL DATA
IN74HCT00A
Quad 2-Input NAND Gate
High-Performance Silicon-Gate CMOS
The IN74HCT00A may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The IN74HCT00A is identical in pinout to the LS/ALS00. * TTL/NMOS-Compatible Input Levels. * Outputs Directly Inferface to CMOS, NMOS and TTL. * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A
ORDERING INFORMATION IN74HCT00AN Plastic IN74HCT00AD SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
Inputs A L L PIN 14 =VCC PIN 7 = GND H H B L H L H Output Y H H H L
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IN74HCT00A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IN74HCT00A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 1.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 10 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 40 A A V Unit
VIH VIL VOH
Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT= VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA
4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
V V V
VOL
Maximum Low-Level Output Voltage
VIN=VIH IOUT 20 A VIN=VIH IOUT 4.0 mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A
ICC
-55C 5.5 2.9
25C to 125C 2.4
mA
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IN74HCT00A
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF, Input tr=tf=6.0 ns)
Guaranteed Limits Symbol tPLH, tPHL tTLH, tTHL CIN Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 19 15 10 85C 24 19 10 125C 28 22 10 Unit ns ns pF
Typical @25C,VCC=5.0 V 15 pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM (1/4 of the Device)
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